Hello to Everyone!
There are updates to the code of the Lattice FPGA and FX3 USB microcontroller.
There were samples losses in high input/output or CPU load situations. We added a slave FIFO buffer in FPGA, changed Cypress GPIF design and now continuous capturing become more stable in real apps. Now thanks to slave FIFO buffer the samples are accumulated in FPGA and then the FX3 microcontroller downloads bulk of data when FIFO contains necessary number of samples.
We captured long signal sample and processed it by Matlab code. Alright, the SNR value is about 50 dB all the time.
The NUT2NT+ and antenna used in test above and oscilloscope used to debug the FPGA code.
Strategic management, design of antennas
Hardware design, manufacturing and testing
Software development, embedded and signal processing
RF circuits design, RA antennas LNA and NUT2NT+ board's RF circuits
Software engineering, C/C++ Developer, NUT2NT+ GNSS-SDR support
Supply and fulfillment management
FPGA Design and Verification Engineer, FAE
FPGA code design
Metal parts design