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Note: No printed manual is included. This document is the primary reference.
BOOT0 is located on the top of the device. It is used to enter ROM download mode for USB wired flashing. For factory reset options, see Chapter 4.The 4 ports are located on the same side of the device, named PA, PB, PC, and PD in sequence. The housing at both ends of the port array is marked with "A" and "D" for orientation reference: the port closest to "A" is PA, the port closest to "D" is PD, and the two ports in between are PB (adjacent to PA) and PC (adjacent to PD).
To simplify wiring, the device’s pin layout, connector key position, and flying lead colors follow a strict, absolute one-to-one correspondence. Refer to the table below when making connections:
| Wire Color | Port A | Port B | Port C | Port D |
|---|---|---|---|---|
| Red | PA00 (Pin 1) | PB00 (Pin 11) | PC00 (Pin 21) | PD00 (Pin 31) |
| Brown | PA01 (Pin 3) | PB01 (Pin 13) | PC01 (Pin 23) | PD01 (Pin 33) |
| Green | PA02 (Pin 5) | PB02 (Pin 15) | PC02 (Pin 25) | PD02 (Pin 35) |
| Blue | PA03 (Pin 7) | PB03 (Pin 17) | PC03 (Pin 27) | PD03 (Pin 37) |
| Black (×4) | GND (2/4/6/8) | GND (12/14/16/18) | GND (22/24/26/28) | GND (32/34/36/38) |
| Port | Available Modes | Factory Default |
|---|---|---|
| PA | Logic Analyzer | Logic Analyzer |
| PB | Logic Analyzer · Vtarget + UART + SReset | Logic Analyzer |
| PC | Logic Analyzer · BMP SWD/JTAG | SWD/JTAG |
| PD | Logic Analyzer · FPGA XVC · Counter Lo @ 132 MHz · Counter Hi @ 132 MHz · GPIO Direct (125 Hz / 250 Hz / 500 Hz / 1 kHz) | Logic Analyzer |
Note: Operating modes are configured and switched through the web interface. Select the required mode before wiring or using a port.
| Pin | Wire Color | PA | PB | PC | PD |
|---|---|---|---|---|---|
| PX00 | Red | CH0 | CH4 | CH8 | CH12 |
| PX01 | Brown | CH1 | CH5 | CH9 | CH13 |
| PX02 | Green | CH2 | CH6 | CH10 | CH14 |
| PX03 | Blue | CH3 | CH7 | CH11 | CH15 |
Note:
Xrepresents the port letter A/B/C/D.
| Pin | Wire Color | Function | Description |
|---|---|---|---|
| PB00 | Red | TX | Device transmits, target receives |
| PB01 | Brown | Vtarget | Used to sense/measure the target board's voltage |
| PB02 | Green | RX | Target transmits, device receives |
| PB03 | Blue | SReset | Connected to the target board's RESET pin to manage target resets |
The Port C supports both JTAG and SWD interfaces for ARM Cortex MCU debugging with automatic detection (JTAG connection is attempted first, reverting to SWD if unsuccessful).
| Pin | Wire Color | Function | Description |
|---|---|---|---|
| PC00 | Red | TDO | Test Data Output |
| PC01 | Brown | TCK | Test Clock |
| PC02 | Green | TMS | Test Mode Select |
| PC03 | Blue | TDI | Test Data Input |
| Pin | Wire Color | Function | Description |
|---|---|---|---|
| PC00 | Red | NC | No Connection |
| PC01 | Brown | SWCLK | Serial Wire Clock |
| PC02 | Green | SWDIO | Serial Wire Debug Data Input/Output |
| PC03 | Blue | NC | No Connection |
The Port D supports AMD (Xilinx) FPGA XVC protocol for programming and debugging via Vivado.
| Pin | Wire Color | Function | Description |
|---|---|---|---|
| PD00 | Red | TDO | Test Data Output: Receives serial data from the target FPGA |
| PD01 | Brown | TCK | Test Clock: Drives the JTAG clock signal to the FPGA |
| PD02 | Green | TMS | Test Mode Select: Controls the FPGA's JTAG state machine |
| PD03 | Blue | TDI | Test Data Input: Transmits serial data into the target FPGA |
When Port D is configured as a signal generator, it functions as a signal output source for clock injection or circuit excitation. Depending on your target requirements, you can select one of the three sub-modes below.
| Pin | Wire Color | Function | Output Frequency |
|---|---|---|---|
| PD00 | Red | Bit 0 | ~66 MHz |
| PD01 | Brown | Bit 1 | ~33 MHz |
| PD02 | Green | Bit 2 | ~16.5 MHz |
| PD03 | Blue | Bit 3 | ~8.25 MHz |
| Pin | Wire Color | Function | Output Frequency |
|---|---|---|---|
| PD00 | Red | Bit 4 | ~4.13 MHz |
| PD01 | Brown | Bit 5 | ~2.06 MHz |
| PD02 | Green | Bit 6 | ~1.03 MHz |
| PD03 | Blue | Bit 7 | ~0.52 MHz |
Voltage limits: The recommended operating voltage range is 1.2 V–3.3 V. Each port is equipped with ESD protection to withstand transient overvoltage, but continuous input exceeding 3.3 V is not recommended.
Adjustable voltage: The target board reference voltage (VTref / VIO_VAR) is controlled by the device’s PWM output and can be configured through the web interface without requiring an external power supply.
Common ground requirement: Regardless of the operating mode, the target board GND must be connected to the ESP32JTAG via the black wire in the cable assembly.
No hot-plugging: Do not insert or remove the cable assemblies while the device or target board is powered; doing so may cause ESD damage.
Power off before wiring: It is recommended to complete all wiring with power removed, then verify all connections before applying power.
The ESP32JTAG is ready to use immediately after power-on — no driver installation is required. The device automatically broadcasts a Wi-Fi hotspot, and all configuration can be completed through the built-in web interface accessed via a browser. This chapter covers how to power on the device, connect to the hotspot, and access the web interface.
| Field | Description |
|---|---|
| AP mode | The device is currently in AP mode, acting as a Wi-Fi hotspot |
| IP | Web interface address; fixed at 192.168.4.1 in AP mode |
| SSID | Hotspot name |
| PSWD | Hotspot password |
| XVC:2542 | XVC server port, used by FPGA tools such as Vivado |
| GDB:4242 | BMP GDB server port, used by debuggers such as Cortex-Debug |
| PA / PB / PC / PD | Current operating mode of each of the four physical ports |
Note: The characters after the underscore in the SSID (
XXYY) are the "device suffix", the last 2 bytes of the device’s MAC address. The suffix is unique to each unit and is also shown on the LCD.
esp32jtag-XXYY. The device shown in the figure has the suffix 999D.esp32jtag to complete the connection.Note: After connecting to the device hotspot, your computer will temporarily lose access to its previous network. This is expected behavior.
https://192.168.4.1 in the address bar and press Enter.adminadminLogin to enter the main web interface.After logging in, five functional tabs are displayed at the top of the interface, providing access to all device operations.
| Tab | Description |
|---|---|
| System Configurations | Port mode configuration, Wi-Fi settings, and advanced options. Default landing page. |
| Logic Analyzer | Logic analyzer waveform capture and viewing |
| UART Web Terminal | Serial terminal for sending and receiving UART data directly from the browser |
| Firmware Update | Over-the-air (OTA) firmware upgrade |
| ESP32JTAG HELP | Built-in user guide |
Note: At this point, the device has completed its initial setup and is ready for use.
By default, the ESP32JTAG operates in AP mode, which requires your computer to switch to the device’s hotspot in order to access the web interface. After switching to Station mode, the device joins your existing Wi-Fi network, allowing your computer to access it directly without changing networks — this is the recommended way to use the device on a day-to-day basis. This chapter starts from the AP mode state at the end of the previous chapter and walks through switching to and configuring Station mode.
System Configurations → Wi-Fi Configuration.ST mode and enter the SSID and password of your local Wi-Fi network.Save settings & Restart and wait for the device to apply the configuration.Note: ESP32JTAG currently supports 2.4 GHz Wi-Fi only.
If the device does not appear on your network after switching to Station mode, check the SSID and password first. If you cannot access the web interface, restore factory settings using the procedure in Chapter 4 to return the device to AP mode.
The ESP32JTAG supports fully wireless firmware upgrades. The entire process requires no USB cable and can be completed entirely through a browser. This chapter covers how to check the current firmware version, obtain new firmware, perform the upgrade, and recover from unexpected situations.
Open the web interface, navigate to the System Configurations tab, and scroll to the Version Information section at the bottom of the page.
Alternatively, the top of the Firmware Update tab displays a concise summary of the current firmware (e.g., Current firmware: 0.2.0 (build Apr 3 2026 16:54:59 commit 41f3034)), making it a convenient way to confirm the version before upgrading.
Firmware releases are available at https://github.com/EZ32Inc/esp32jtag_firmware/releases
Each release contains two files, distinguished by their filename suffix:
| File Suffix | Purpose |
|---|---|
_ota.bin | For OTA wireless upgrades only — use this file for the procedure in this chapter |
_full.bin | Factory flashing / USB wired flashing — use only in emergency recovery scenarios |
Example filename format: esp32jtag_v0.2.0_20260403_165459_41f3034_ota.bin, which encodes the version number, build timestamp, and Git commit in sequence for easy version comparison.
Caution: Do not use
_full.binfor OTA upgrades. The OTA process only accepts_ota.bin; uploading the wrong file will cause the upgrade to fail.Note: The device does not check for updates automatically. Users must download the firmware manually and upload it themselves.
Firmware Update tab in the top navigation bar of the web interface._ota.bin file into the dashed box in the center of the page, or click the box to manually select the file.Upload & Update button. A progress bar will appear and display the upload status in real time.Version Information section.Caution: Do not cut power during the upgrade process. If the upload is interrupted mid-way, the device retains the original firmware and can be safely retried.
If you need to clear all configuration and restore the device to its factory state (Wi-Fi returns to AP mode, all port configurations are reset), there are two methods:
Method 1 (Recommended): Via the Web Interface
On the System Configurations page, click the Set to default button. After confirmation, the device automatically clears all configuration stored in Flash and reboots.
Method 2: USB Wired Flashing
If an OTA failure causes firmware corruption or the device enters a boot loop, the web interface will be inaccessible. In this case, recovery must be performed using the browser-based one-click flashing tool.
Use Chrome or Edge for this procedure. The WebSerial flashing tool requires Web Serial support, which is not available in Firefox or Safari. Also make sure the USB-C cable supports data, not only charging.
https://adafruit.github.io/Adafruit_WebSerial_ESPTool/. Click the Connect button on the page.COM3 etc.; Mac shows cu.usbserial), then click Connect. The page will automatically detect the chip.Offset field, enter: 0x0.Choose a file and select your esp32jtag_vXXX_full.bin file from the dialog.Caution: You must use the
_full.binfile here. It is a complete Flash image including the bootloader and partition table. The_ota.binfile is not valid in this mode.
Program button and wait for the process to complete.esp32jtag-XXYY hotspot, open https://192.168.4.1, and verify the firmware version in the web interface.