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Check out the the latest Atum A3 Nano design examples in GitHub:
This is the default configuration bitstream for the Atum A3 Nano board, demonstrating some of its basic features.
This is a Verilog HDL design example that demonstrates HDMI video output on the Atum A3 Nano board.
This is a Verilog HDL design example that tests the 64MB SDRAM on the Atum A3 Nano board.
This is a Verilog HDL design that demonstrates a UART loopback test on the Atum A3 Nano board.
A trusted, pre-configured Quartus template project for the Atum A3 Nano, providing a correct hardware configuration starting point to accelerate development.
A Nios V processor-based design example demonstrating how to sequentially display bitmap image files from a Micro SD card on an HDMI monitor.
A Nios V processor-based design example demonstrating how to read from and write to an SD card on the Atum A3 Nano.
The CE certification is taking a bit longer than expected. We are actively working with a third-party testing laboratory to complete the process. While we don’t have a confirmed completion date yet, we are holding weekly meetings with them to expedite the certification so we can start shipping to Europe as soon as possible. We will send another update when we have better estimate of delivery dates.
Atum A3 Nano is part of Altera Innovation Lab
Altera Agilex 3
·
A3CZ135BB18AE7S
· FPGA
Largest Agilex 3 FPGA with 135K logic elements