Over the past six months, we’ve made significant progress on sSDR. Two intermediate board revisions have been built and tested, and the final production-revision samples are now in manufacturing.

Early measurements on the Rev1 board showed solid performance up to 8.5 GHz, but we wanted to extend the range into the X-band. This led us to redesign the RF matching network and move to components optimized for 11 GHz and above.

Rev1 used the LMS8001B (high-linearity variant). In Rev2, we evaluated both LMS8001A and LMS8001B. With its integrated LNA and PA, the LMS8001A lets sSDR pick up much weaker signals and deliver significantly higher transmit power.

Rev2 Highlights

• Switched from MHF4 to MHF7S connectors (rated up to 15 GHz).
• MPW2024 versions of LMS8001A/B.
• Improved clock-distribution circuitry.
• Finalized RF-matching improvements for operation above 11 GHz.

TX output power vs. frequencies (dBm, PA mid range)

RX input power vs. frequencies (dBFS)

Two graphs on these plots representing the LMS8002 up/down converter and the LMS8002 bypass mode.

Upgraded PCIe Performance

We also discovered that some SBCs expose only a single PCIe lane (notably the Raspberry Pi 5) and pairing that with a 7-series FPGA limits PCIe Gen2 throughput to around ~52 MSPS MIMO. Since PCIe Gen3 is now common across most platforms, we upgraded to the modern UltraScale+ family with 12.5-GT/s transceivers. This upgrade not only unlocks higher PCIe bandwidth but also enables future support for 10GbE and even over-fiber operation.

The XCAU7P also offers roughly three times more logic resources than the XC7A35T while supporting full x4 PCIe connectivity. To take advantage of all four lanes, we switched to an M.2 Key M interface. The extra bandwidth benefits both complex FPGA processing and GPUDirect.

Rev3 Highlights

• Replaced XC7A35T with XCAU7P UltraScale+ FPGA.
• Updated USB2.0 PHY (USB3333 → USB3317).
• Upgraded QSPI flash from 32 Mbit → 128 Mbit.
• Updated PMIC for UltraScale+ power requirements.
• Adopted M.2 2242 Key M to support PCIe 3.0 ×4 for maximum performance.

What’s Next

Initial Rev2 testing is complete, final design tweaks are in, and Rev3 is now in manufacturing.
In parallel, we’re preparing the sSDR crowdfunding campaign to go live soon.

Stay tuned—more updates are on the way!