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Dec 19, 2019

Field Report: Running a RISC-V SoC on FireAnt

by Thomas H

The announcement for the FireAnt board campaign launch caught my eye because I had not heard before of the T8 FPGA at its core. I backed the campaign and, eventually, my board was delivered. I decided to see if I could implement my “Bonfire” RISC-V CPU Core/SoC on it.

As a starting point, I used a small top-level framework I built some time ago: the Bonfire Basic SoC. It is meant as an SoC for these kind of implementations and also for simulations.

My cores are all built with FuseSoC. Of course, there is no FuseSoC backend for the Effinity IDE yet, so I just copied a build directory of a GHDL simulation run into the Efinix project.

For the FireAnt, I created a bonfire_basic_soc_top.vhd. One task of this top entity is to configure the on-board memory. Effinity is not able to synthesize the normal MainMemory entity of the Bonfire SOC, because of the lack of byte lane write-enables in the Trion block RAMs. So I added a “laned” memory which is constructed from RAM8 entities.

Basically it took me a few hours to get the project running. Aside from being quite limited in RAM, turns out the T8 FPGA is quite capable of running a 32 bit Soft-CPU, which consumes about 57% of the logic elements of the T8. Compared to Xilinx Series 6 or 7 FPGAs, the T8 runs at only about 25% of the clock-rate. But the overall implementation experience was smooth, I like the simplicity of Trion Series FPGAs.

More details can be found in the readme file of the project repository.

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