Ceres is an FPGA development board built around the biggest and fastest FPGA available that doesn’t require a paid EDA tool license. It plugs into a PCIe Gen3 x8 slot, accepts up to 32 GB of DDR4 memory, and features a versatile AMD Kintex™ UltraScale+™ FPGA chip at its heart.

It is engineered to expose as much I/O to the user as possible through its array of QSFP28, SYZYGY TXR4, and SYZYGY STD ports. Ceres is a single board that can handle a wide range of high-bandwidth scenarios, including 100 Gigabit Ethernet or DisplayPort 2.1. Its robust power delivery system lets Ceres handle almost any soft processor design.

High-Performance, High-Bandwidth

Ceres has a robust, performant design that makes it great for tasks like machine learning inference, high-speed networking, data acquisition, video processing, and computer architecture research.

Eight serial transceivers with up to 28 Gbps each are exposed through a QSFP28 cage and a SYZYGY TXR4 port. They accept commercially available 100 Gigabit Ethernet QSF28 modules and SYZYGY transceiver pods, and allow experimenting with high-speed transceiver pods of your own design.

Two SYZYGY STD ports make Ceres compatible with a wide range of existing peripherals, including Avnet’s line of high-bandwidth ADC and DAC Zmods.

Features & Specifications

• AMD Kintex™ UltraScale+™ XCKU5P-2FFVB676 FPGA (474k logic cells)

I/O

• PCI Express Gen3 x8 edge connector (potentially Gen4 capable with custom IP)
• 260-pin SODIMM slot for up to 16 GB DDR4-2400 or 32 GB DDR4-2133 DRAM
• zQSFP+ (QSFP28) cage for up to 100 Gbps Ethernet
• SYZYGY TXR4 port with four 28 Gbps lanes and 14 high-density I/O
• SYZYGY STD port with 32 high-performance I/O as 16 differential pairs
• SYZYGY STD port with 32 high-density I/O

Programming and Debugging

• 128 Mbit QSPI Flash with Tag-Connect TC2030 programming header
• 14-pin JTAG header compatible with AMD and Digilent
• Debuggable over PCI Express using AMD Virtual Cable and Hardware ICAP

Form Factor

• Full-height, half-length PCI Express (111 x 168 mm, 4.3 x 6.6 in)

Open Source

Ceres is open-source hardware, released under the CERN-OHL-P-2.0 license. The hardware repository on SourceHut contains KiCad design files as well as schematics, board layout, BOM, as well as an XDC file with I/O constraints.

Open-source gateware and firmware for Ceres are available under the MIT License. The gateware repository on SourceHut contains projects with AMD Vivado™ development tools and AMD Vitis™ design suite for bringup testing and validation, and will eventually contain sample designs using LiteX and Amaranth.

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