Retro-uC

An open silicon microcontroller with a Z80, MOS6502, and M68K - start the open silicon revolution

Oct 17, 2018

First time right, QFP package details and test material

After a good start the campaign is going slower now. We are over half way and 17% of the funding goal is reached. It is time now to back this project if you want it to succeed.

In this update I will discuss how first time right was taken as target for the Retro-uC project from the start; the details on the QFP package of the Retro-uC chip and the

First time right

A second source of comments on the Retro-uC campaign was about the fact the project assumes the chip will work the first time; in the industry also known as first-time-right. This goal has been taken into account during the definition of the Retro-uC project from the start. It was performed by applying the KISS principle at several levels of the project:

A more detailed explanation can be found on a blog post on chips4makers.io

QFP package

The package for the Retro-uC chip has been finalized. It will be a 100-pin QFP package of 14mm x 20mm. The details can be seen in the next picture:

You can see that this package is rectangular and has a 0.65mm pitch of the pins. A square version with a higher pin pitch was not available as open tool. Making a custom package would need more than $10 000 extra for the tooling start-up costs.

Also a preliminary pin list is given in the next table:

PinNet
1VCORE
2GND
3GND
4VIO
5-26PA1-PA22
27VIO
28GND
29GND
30VCORE
31-50PB1-PB20
51VCORE
52GND
53GND
54VIO
55-76PC1-PC22
77VIO
78GND
79GND
80VCORE
81-89PD1-PD9
90TDI
91TDO
92TCK
93TMS
94TRST_N
95RESET_N
96CLK
97I2CBOOT
98ENM68K
99ENZ80
100EN6502

VCORE is the supply for the logic on the chip and has to be 3.3V; VIO can be chosen to be 3.3V or 5V to have 3.3V or 5V I/O. It still need to be finalized how the input and outputs of the peripherals are shared with the I/O pins on the chip. An update of the pin list will be given when this is done.

Development test material

In order to test the peripherals on the Retro-uC I ordered some chips to allow testing the implementation on an FPGA. You can see the chips I got in the next picture:

You find the next chips on this photo (from left to right):

These chips are meant to test the I2C boot feature of the Retro-uC and also for investigating the possibility of providing a SRAM interface on the pins of the Retro-uC. When successful it allows to have external memory extra to the 4 kB on chip memory or usable for other memory mapped access to external devices. This is a feature often requested that should allow to use the Retro-uC also as a microprocessor and not only as a microcontroller. I do think this feature should be able to be implemented without risk of messing up the rest of the chip so I am willing to make a compromise on the minimal number of features strategy to reach first time right for the Retro-uC. In one of the next updates it will be announced if this feature will be added to the Retro-uC.


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