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Project update 2 of 53
LimeSDR Mini 1v0 PCB drawing (top)
As noted in the previous update, we have made a number of improvements to the LimeSDR Mini design since the initial prototypes, including changing the MMCX RF connectors to SMA, adding a U.FL connector for external clock input, and further optimising the RF matching networks.
We are now pleased to announce that the LimeSDR Mini PCB design database and FPGA gateware RTL sources have been published to GitHub:
Host driver support is provided via the same Lime Suite and SoapySDR stack as used with the sibling LimeSDR USB and LimeSDR PCIe boards, providing a consistent API experience.
An order has been placed for a small run of pre-production boards and we should have these back in a few weeks time, to allow for further testing before going into full production.
Stay tuned for further updates!
Andrew and the LimeSDR Mini Team