Open-V

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Dec 07, 2016

5th RISC-V Workshop

We (Elkim and Ckristian) spent last week in the Bay Area attending the 5th RISV-V Workshop and meeting with a bunch of people in the industry. This first update reports some of the interesting things to came out of this trip.

Thank You!

Before we get into the trip report, we want to give a big thank you to everyone who has supported us so far! So far, over 200 of you have backed the campaign. There are backers representing 31 countries, over 57% of them from outside the US, which we think shows the need and desire for open silicon is truly universal.

This is an ambitious campaign with a high funding goal, but we are working hard to make sure we succeed. There’s exciting news coming and we will keep you all informed with regular campaign updates like this one. In the meantime, please help us by telling other people about the campaign. Of course, if you haven’t yet backed the campaign, please do that too!

RISC-V Workshop

The 5th RISV-V Workshop was hosted at Google in Mountain View, California. It was a great two days of presenting, learning, strengthening old collaborations, and building new ones. Here are our big take aways.

RISV-V Has Momentum

The conference was standing room only, with probably close to 375 people attending. This up almost 50% from the 4th RISV-V Workshop held just six months ago. It’s been amazing to see how the community and technology have grown in such a short time.

One of the attendees and presenters, Ron Minnich from Google, summed it up well in a quote that appeared in an EE Times article about the workshop:

“This event has the same feel to me as the early Linux gatherings in the 1990’s. You could tell something was happening, but you didn’t know where it was going to go, just that things were going to change.” – Ron Minnich

Silicon is King

Standards and simulations are important, but nothing beats seeing real hardware. We were blown away by how many groups announced and/or showed real silicon at the workshop. While the idea of being the lone pioneering group bringing real RISC-V silicon to the world is certainly romantic, we’re actually much happier and relieved to see many groups pushing these boundaries at the same time. Some of these projects, like PULP, are still experimental and reside mostly in labs. Others, like SiFive, are nearly ready to ship. (More on SiFive below.)

No One Else is Doing Analog

Of everyone working on bringing to life real RISC-V silicon, we’re the only ones working on open source analog peripherals. Everyone else is either avoiding analog altogether or licensing proprietary IPs. This is because analog peripherals are generally much more difficult to design and do not translate well across different processes or nodes. For example, an ADC designed for a 130 nm process needs a lot of modification to work at a 65 nm process and, reglardless of the node, the ADC cannot be easily run on an FPGA.

Peripherals also need a bus connector, something like a decoder that can translate data into and out from buses. Right after the 5th RISC-V Workshop, we visited REUSE 2016 and discussed peripheral IP with different semiconductor vendors. These discussions confirmed what we already knew - licensing the IP for analog components is expensive. For example, the upfront licensing cost is about $20,000 for a PLL and about $15,000 for an ADC, not including royalties charged by the foundry. Using such IPs leaves you blind with a blackbox until the foundry merges the final layout during tapeout.

Even creating a microcontroller without a bunch of analog peripherals still requires a lot of analog-like circuitry. You need clock generation and distribution, analog and digital I/O, data converters, biasing, regulators, and other such “analogish” blocks to get a full-featured microcontroller. We are one of the only groups actively working to create open and understandable analog blocks. In fact, open analog peripherals are such the exception that the EE Time article previously mentioned mistakenly overlooked the Open-V and noted:

“A significant last mile hurdle stands in the way of anyone wanting a completely open source processor. There are no open source analog or mixed-signal blocks, and foundries have patents associated with their standard cell and I/O libraries.”

We’re in touch with the author and hope to show off the analog peripherals we’ve been working on. Nonetheless, the point is valid - analog peripherals are the last major barrier to truly free microcontrollers. We’re tackling that problem head-on.

Security is a Killer App

Security emerged as one of the main themes of the workshop. As it turns out, there is very little hardware you can trust to be secure. The situation is so bad that builing an entire hardware ecosystem from scratch seems to be only viable option at this point. Enter RISC-V. Security as a byproduct of openness might be the main reason RISC-V gains market share. The urgency of securing the Internet of Things will only accelerate this trend. We have been working for a couple of years on low-power/low-die area algorithms to implement key-exchange mechanisms and True-Random Number Generator (TRNG) blocks. You will hear more on this on an update. And, yes, we are considering adding some of this funcionality to the Open-V micro – stay tuned.

Collaboration and Competition

As already noted, more and more members of the RISC-V community are pushing harder and harder to expand what RISC-V can do and to bring actual chips to market. Naturally, some efforts will overlap and people need to decide whether they will primarily compete or collaborate. This workshop illustrated clearly that the RISC-V community values collaboration over competition, which is far from the norm in the semiconductor industry.

SiFive

We’d already been in touch with several other teams before the workshop and have begun talks with several more thanks to the workshop. Of particular note is SiFive and their HiFive1 development board, also currently on Crowd Supply. We (and probably they too!) are getting a lot of questions about how our projects compare. At a high level:

  • The CPU core at the heart of the HiFive1’s microcontroller (the Freedom E310 chip) is very similar to the CPU core at the heart of the Open-V.
  • The Freedom E310 uses an open CPU and some other peripherals, but uses proprietary analog IPs, whereas the Open-V is fully open.
  • The Open-V is based on a TSMC 130 nm process. The Freedom E310 is based on a TSMC 180 nm process.
  • Other than the different processes, the Open-V peripherals could be used in the Freedom E310.
  • SiFive’s HighFive1 will ship in the next month or so, but it’s not clear if or when the Freedom E310 chips will be for sale. SiFive’s main business model seems to be to make custom chips based off the reference design, not selling chips of their own.
  • SiFive is a venture-backed company. OnChip is a research team growing organically into a spin-off.

These differences and similarities are actually quite complementary and we’re already in talks with SiFive about how we might collaborate for everyone’s benefit. Nothing’s yet decided, but we’ll keep everyone updated as things progress!

Arduino

We met at the workshop with a couple of people from the Arduino world. A RISC-V microcontroller is definitely interesting to them. Again, we’re speaking with them and will update everyone once we have something definite. In the meantime, some fun trivia: the inventor of Arduino, Hernando Barragán, is from Colombia!

Spread the Word!

If you’ve read this far, you must be interested in what we’re doing. We have a great team of people working on Open-V, but we’re relatively unknown, we’re not backed by a powerful company or large grant, and we need a lot of help to get this effort off the ground and get real, open RISC-V silicon into people’s hands. Please back our campaign and help spread the word. Every little bit counts.

Thanks,
Elkim and the OnChip Team

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Credits

OnChip

With over 30 years of cumulative experience in analog, digital, and RF circuit design, the OnChip team aims to contribute to the growth of the open source community by developing open silicon.


Luis Rueda

MSEE, Analog Design

Javier Ardila

BSEE, Mixed Signal Design

Rodrigo Gómez

BSEE, Analog Design

Héctor Gómez

MSEE, Digital Design

Wilmer Ramírez

BSEE, Digital Verification

Andrés Amaya

MSEE, Mixed Signal Design

Rolando Torres

MSEE, Mixed Signal Design

Camilo Rojas

BSEE, Digital Design

Ckristian Durán

MSEE, Digital Design

Élkim Roa

PhD, Mixed Signal Design


OSH Park

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