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Nov 16, 2017

Project update 5 of 21

Killing the Noise

Well, it’s been an exciting week for the Haasoscope! The project went live, and we are already 1/3 funded in just 2 days!

First, thanks to all of you who’ve pledged support already! You can also help the project by spreading the word to others that might be interested - a post, tweet, what have you.

As you know, the board is already in good shape, but I’ve continued to "refine" it lately. For instance, killing noise. You may have noticed that some of the prototypes’ screenshot’s waveforms were a bit noisy. Fear not - it’s being solved! I’ve already tracked the majority of the noise down to how I was producing the DC offsets. Switching to a low-noise DAC solved the majority of the problem, along with some extra filter caps. The remaining noise levels can be seen here:

This is already pretty good - just 1-2 bits of noise, but I think we can do even better. What’s neat is we can use the Haasoscope to analyze itself! Here’s an FFT of the noise on a channel, taken with the Haasoscope:

You see the peaks at 25 and 50 MHz? Those are harmonics of the FPGA and ADC clocks (50 MHz and 125 MHz,respectively)! This is a typical issue in high-speed digital boards - those high frequencies are easy to inductively couple to other signals. The best way to solve it is with a proper ground plane - a solid layer of copper just under those signals, allowing the return currents to flow right next to the signal. This minimizes the loop area, which limits the magnetic fields, and thus limits inductance. E&M baby! To get a nice ground plane means going to a 4-layer PCB, so there’s room for the ground plane, power distribution, and signal traces. I ordered a 4-layer prototype last week, so by the end of the month, we’ll know how it performs.

Take care, and thanks again for supporting this project!
Best, Andy.

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