Integer Boundary Spurs

When we designed ERASynth Micro, we had to optimize the cost. Initially we were planning on using a triple loop PLL architecture similar to its predecessor ERASynth. Later we decided to use a dual loop architecture for two main reasons:

1. To keep the final device cost below $250.
2. To be able to power it using a USB 2.0 port.

So, we decreased the loop count to two and were able to realize the above goals. However, there were some trade-offs. With a dual loop PLL, we had to operate the main PLL in fractional mode. Fractional PLLs exhibit very large spurious artifacts when output frequency is close to an integer multiple of the PFD rate. We did a few tests to see IBS performance of LMX2572 which is the main PLL IC in ERASynth Micro. The results were surprisingly good. In fact LMX2572 performs better than its big brother LMX2594 when it comes to integer boundary spurs. Please see the following images for test results:

ERASynth Micro Integer Boundary Spurs @ Fout: 6.000001GHz (6GHz + 1kHz)

LMX2594 Eval Board Integer Boundary Spurs @ Fout: 6.000001GHz (6GHz + 1kHz)

ADF5355 Eval Board Integer Boundary Spurs @ Fout: 6.000001GHz (6GHz + 1kHz)

ERASynth Micro Integer Boundary Spurs @ Fout: 6.00001GHz (6GHz + 10kHz)

LMX2594 Eval Board Integer Boundary Spurs @ Fout: 6.00001GHz (6GHz + 10kHz)

ADF5355 Eval Board Integer Boundary Spurs @ Fout: 6.00001GHz (6GHz + 10kHz)