Funding ends on Feb 20, 2017 at 03:59 PM PST (11:59 PM UTC)
"The 2x2mm chip will be made in a 130nm process and aims to be the equivalent of commercial microcontrollers implemented with an ARM M0 core."
"If you want to get your hands on one of these open microcontrollers, the Crowd Supply campaign is actually fairly reasonable, considering this is custom silicon."
"It will have 8k of SRAM and will be capable of running at up to 160MHz. Other features include two PLLs, two 10bit A/D converter channels, two 12bit D/A channels and 16 GPIO pins."
"Did you ever think it would be great if hardware was open to the transistor level, not just the chip level?"
"...promising us new, better, more open and more free systems on which to build our information age."
"The RISC-V (pronounced “Risk Five”) is a fully open source, open silicon microcontroller architecture that anyone can use to design, manufacture, and sell RISC-V chips and software."
"OnChip—founded by a group of doctoral students—is targeting its Open-V microcontroller at IoT applications and is aiming to offer performance similar to the ARM Cortex-M0 microcontrollers."
"Siendo la primera implementación comercial en un chip libre de la arquitectura, este Microcontrolador RISC-V open source de 32 bits busca competir con los controladores basados en ARM M0."
The OnChip Open-V microcontroller is a completely free (as in freedom) and open source 32-bit microcontroller based on the RISC-V architecture. The Open-V has a host of built-in peripherals you’d expect of any modern microcontroller and was designed to compete with the capabilities of ARM M0-based microcontrollers. This crowdfunding campaign will bring the Open-V into mass production and make it widely available to anyone. If you love hacking on embedded controllers, breaking down closed-source barriers, having the freedom to learn how things work even down to the transistor level, or have dreamed of spinning your own silicon, then this campaign is for you and we need your help!
The Reduced Instruction Set Computing (RISC) paradigm has been around for decades and many processors fall into this category. RISC-V (pronounced “risk-five”) is a particular implementation of RISC concepts as an open source instruction set architecture (ISA). Although the RISC-V standard has been around (and evolved) since 2010, it has never been used in a chip available on the open market. Some chips have been manufactured using RISC-V, but they have been relegated to the research lab and academia. We’re going to change that. With the OnChip Open-V, for the first time ever, you will be able to purchase a RISC-V-based chip and use it in real projects and products. This isn’t just a one-time thing - we’re planning on keeping the Open-V in production for as long as there is demand. Our initial manufacturing run will produce approximately 70,000 chips.
An Open-V bare die
We’ve open sourced all files for the entire OnChip Open-V design, including the register-transfer level (RTL) files for the CPU and all peripherals and the development and testing tools we use. These sources are available under the MIT license from our GitHub account.
We think open source integrated circuit (IC) design will give the semiconductor industry the reboot it needs to get out of the deep innovation rut dug by the entrenched players. Just like open source software ushered in the last two decades of software innovation, open source silicon will unleash a flood of hardware innovation. The Open-V microcontroller is one concrete step in that direction.
With open silicon, you can:
A bare Open-V die wire bonded to our OSH Park test board
In this campaign, you can order the Open-V chips themselves and a development board we’ve designed around the Open-V chip.
The dev board comes completely assembled.
Render of the Open-V dev board
The Open-V core is Arduino-compatible, which means you will benefit from the abundant resources of the Arduino community. As we make progress toward manufacturing the first batch of Open-V chips, we will release demos showing how Open-V can be used with the Arduino toolchain and other resources.
Of course, the Open-V chip can be used completely independently from the Arduino ecosystem. For example, the RISC-V ecosystem is rapidly growing and immediately applicable for Open-V development.
Many commercial microcontrollers feature proprietary, licensed instruction sets. Licensed instruction sets and microprocessor cores restrict the process of modifying the core for different purposes such as improving performance and adapting it to specific applications.
RISC-V is a new open instruction set architecture (ISA) designed by the Berkeley Architecture Group with the aim to support architecture research and education. RISC-V is fully available to public and has advantages such as a smaller footprint size, support for highly-parallel multi-core implementations, variable-length instructions to support an optional dense instruction, ease of implementation in hardware, and energy efficiency.
Moreover, because Open-V and RISC-V are open, a curious person will be able to read and modify the register-transfer level (RTL) and propose changes to enhance the performance of Open-V. A maker would be able to understand the architecture by testing the RTL core with FPGAs or simulators. Already, researchers made some interesting RISC-V-based chips unrelated to Open-V.
The OnChip Open-V is the first microcontroller featuring both an open source CPU and open source peripherals. The glue between the CPU and peripherals (i.e., the buses), is also open source, both the specification and the actual implementation. Currently, we have ADC, DAC, SPI, I2C, UART, GPIO, PWM, and timer peripherals designed and tested in real silicon. We are working on other peripherals, such as USB 2, USB3, internal NVRAM and/or EEPROM, and a convolutional neural network (CNN).
The Open-V microcontroller uses several portions of the Advanced Microcontroller Bus Architecture (AMBA) open standard for on-chip interconnection. This makes any Open-V functional block, such as the core or any of the peripherals, easy to incorporate into existing chip designs that also use AMBA. We hope this will motivate other silicon companies to release RISC-V-based microcontrollers using the peripherals they’ve already developed and tested with ARM-based cores.
We think buses are so important, we even wrote a paper about them for IEEE LASCAS 2016.
Power and area simulations show that a RISC-V architecture like that used in the Open-V can be used to replace ARM M0+ microcontrollers with similar performance. The table below shows some comparable chipsets and how they stack up.
|Arch.||ARM M0+||MIPS M4K||ARM M0+||ARM M0+||ARM M0+||16-bit RISC||megaAVR 8-bit||RISC-V|
|IDE||Arduino, IAR, Keil||MPLAB X IDE||Arduino, Atmel Studio||Simplicity Studio||LPCXpresso||Energia, CCS, IAR||Arduino, Atmel Studio||RISC-V toolchain|
|Max Freq.||32 MHz||80 MHz||48 MHz||24 MHz||30 MHz||16 MHz||20 MHz||160 MHz|
|Power||240 μA/MHz @ 4 MHz||700 μA/MHz @ 80 MHz||179 μA/MHz @ 48 MHz||115 μA/MHz @ 24 MHz||110 μA/MHz @ 30 MHz||120 μA/MHz @ 1 MHz||700 μA/MHz @ 8 MHz||167 μA/MHz @ 100 MHz*|
|SRAM||8 KB||32 KB||32 KB||4 KB||1 KB||0.5 KB||2 KB||8 KB|
|Comms||SPI, I2C, JTAG||SPI, I2C, JTAG||SPI, I2C, SDIO, JTAG||SPI, I2C, SDIO, JTAG||SPI, I2C, SDIO, JTAG||SPI, I2C, JTAG||SPI, I2C, JTAG||SPI, I2C, SDIO, JTAG|
|ADC||12-bit 1.1 MS/s||10-bit 500 KS/s||12-bit 350 KS/s||None||None||10-bit 200 KS/s||10-bit 77 KS/s||10-bit 10 MS/s|
|PWM||4 x 16-bit||5 x 16- or 32-bit||8 x 16-bit||6 x 16-bit||2 x 16-bit or 1 x 32-bit||3 x 16-bit||6 x 8-bit||2 x 16-bit|
* Dynamic power measurement condition for Open-V: three while loops executed from SRAM, all peripheral clocks disabled, VDD = 1.2 V, Temperature = 25° C
Notably absent from the Open-V specifications is an internal non-volatile memory. The dev board will ship with an external 32 KB EEPROM, but the Open-V chip itself currently does not have an internal non-volatile memory. We are working to change that and hope to include non-volatile memory in the first batch of Open-V chips, but there are challenges yet to overcome.
Integration of non-volatile memory on regular CMOS technology is a challenge since the intellectual property is controlled by only a few companies and literature is lacking. Similarly, an IP license for NVRAM for pure CMOS has been difficult to find. Just a few companies control this market, their licensing offices are not friendly, and they haven’t yet responded to us as we would hope.
EEPROM will require additional masks and will increase the cost of the mask set, as well as increase the wafer cost. We have designed our own NVRAM, to be really open, and we are aiming to test it in the MPW in March 2017 (see schedule below). We are doing a design effort to get our NVRAM design to accommodate at least a bootloader capable of getting data from an external EEPROM and/or SD Card.
Our wire bonding machine at work
We have over 30 years of cumulative experience designing chips in the semiconductor industry and we believe the industry can do better. We aim to open the door to chip design to a larger community and in so doing drive down the cost of innovation.
The semiconductor industry is today where the operating system and compiler industry was several decades ago: knowledge is concentrated in a small number of specialists using highly inefficient tools whose configuration and parameter tweaking alone take up the vast majority of the time and effort expended. We need to move away from a world in which a team with US- and India-based engineers cost upward of $100,000 per day.
The problem is simple: the people supposedly solving problems in the semiconductor industry are not themselves users of their own solutions. For example, rarely does a chip designer know the end application of the chip they are designing or the company who commissioned the chip in the first place. Similarly, the creators of electronic design automation (EDA) tools (the software used to design new chips) aren’t in the business of designing chips.
The solution is equally simple: spread the knowledge of chip design to those people who actually need a new chip to solve a real problem. The best way to do this is by open sourcing everything from the ground up. This will spur innovation and force existing players to be more competitive.
The OnChip Open-V is a concrete step in this direction. With the Open-V, for the first time, open silicon will be widely available. We hope it will be used in ways we haven’t yet imagined.
An Open-V bare die in a tray
The microcontroller will be manufactured by Taiwan Semiconductor Manufacturing Company (TSMC), who has a lot of experience manufacturing integrated circuits with state-of-the-art features. The development boards will be made and assembled separately.
Our testing board with a wire-bonded Open-V bare die
An analog and digital integrated circuit design is a complex venture, involving architecture design, circuit design, verification, software design, and more. As with any major engineering project, the Open-V carries the risks associated with such complexity. Although rigorous debugging and testing has been and will continue to be exercised throughout this project, there exists the possibility of bugs creeping in. Commercial chips often have bugs, but usually their bugs have a work around that can impact performance but not be a complete showstopper. However, a single unfixable bug is enough to make a chip unusable.
We are confident we can minimize the impact of potential bugs in the following three ways:
While the third parties associated with the project are trustworthy and have a track record of good work, it’s also clear their activities constitute a risk not in our control. Of course, we will keep everyone updated at each milesone and we will be transparent about any problems that might arise.
MSEE, Analog Design
BSEE, Mixed Signal Design
BSEE, Analog Design
MSEE, Digital Design
BSEE, Digital Verification
MSEE, Mixed Signal Design
MSEE, Mixed Signal Design
BSEE, Digital Design
MSEE, Digital Design
PhD, Mixed Signal Design