Open-V

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Jan 25, 2017

Collaboration with SiFive

Today, we’re excited to announce a collaboration with SiFive, a company founded by the creators of RISC-V and dedicated to open source silicon. In the rest of this update, we’ll describe the collaboration in detail, what it means for the Open-V microcontroller, and what it means to you, our supporters.

Ever since SiFive’s HiFive1 campaign was launched just a week after we launched Open-V back in November, we’ve both been getting a lot of questions about how we might collaborate. It’s taken a while, as these things do, but we finally have a concrete answer we think will benefit everyone, not least the RISC-V community. Here’s how we’re collaborating (Update: SiFive has also announced the collaboration on its blog):

Open-V Will Use the SiFive E31 CPU Coreplex

Instead of using the CPU we designed for the Open-V, we are switching to SiFive’s open source CPU, a significant performance upgrade.

All Open-V Peripherals Will Be Compatible with SiFive Chips

While the core of of any microcontroller is the CPU, most of a microcontrollers capabilities lie in its peripherals. This is where the Open-V really shines - its peripherals, especially the analog peripherals, are some of the only open peripherals available in the RISC-V ecosystem. We are working closely with SiFive to make sure the Open-V peripherals can be repurposed for SiFive chip designs. Open-V’s analog peripherals are especially valuable in this regard, as different process nodes require significantly different analog peripheral designs. As a result, we are migrating from our original 130 nm process node to the SiFive Freedom E310’s 180 nm process node. This process node change won’t negatively impact the proposed Open-V performance.

SiFive Will Donate Wafer Space in a May 2017 Tapeout

One of the biggest obstacles to designing silicon is the sheer cost of iterating on designs. Sure, there are good simulations, but in the end you have to turn a raw silicon wafer into a functioning chip to really test your design. Silicon wafers come in a few standard diameters, like 8” and 12”, but not that much area is usually needed when testing a single chip design. That’s why there are multi-project wafer (MPW) services that batch together many small chips onto a single wafer. This works well, but is still expensive.

As it turns out, SiFive had already scheduled an entire test wafer of their own for fabrication in April/May 2017. As part of our collaboration, SiFive is donating some of that extra space to us. This is right in line with our own schedule for testing the Open-V chips and will save us some money.

OnChip Will Contribute to the Free Chips Project

The Free Chips Project is just getting started and is meant to be a repository of open source silicon. All of the Open-V, as well as many of the more experimental peripherals we’re working on outside of Open-V, will be contributed to the Free Chips Project for others, including SiFive, to use.

Benefits of Collaboration

There are four main benefits of this collaboration:

  1. Common Building Blocks: This collaboration is a big step toward the RISC-V community actually reusing common components, like the CPU and ADC, instead of reinventing the wheel for each new chip. This means the components will be better tested, be better supported by the development toolchains, and have a better chance of being improved by the community.
  2. Customized Open-V Chips: SiFive is in the business of making custom RISC-V chips for their customers. Because the Open-V will now be using the SiFive CPU and SiFive will be using Open-V’s peripherals, it should be quite easy for someone using the Open-V chip to work with SiFive to actually make their own version of Open-V to suit their specific needs.
  3. Robust Community: An open source project is only as strong as its community. The simple act of two teams working together makes the entire community more robust and resilient to failure. Thanks to the shared knowledge that naturally arises from collaborative efforts, if one team stops working on an aspect of a project, another team can more easily pick up where the first team left off.
  4. Efficient Use of Resources: This collaboration reduces costs for both OnChip and SiFive. For OnChip, we will save about $80,000 in Open-V development costs and are lowering our funding goal from $480,000 to $400,000. For SiFive, using the Open-V peripherals will save them money in licensing fees and development resources.

We anticipate this partnership growing over time. One avenue we’re discussing is getting to an actual production run of roughly 20,000 chips. We also have other partnerships in the works. Stay tuned!

Abrazos,
Elkim and the OnChip team

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Credits

OnChip

With over 30 years of cumulative experience in analog, digital, and RF circuit design, the OnChip team aims to contribute to the growth of the open source community by developing open silicon.


Luis Rueda

MSEE, Analog Design

Javier Ardila

BSEE, Mixed Signal Design

Rodrigo Gómez

BSEE, Analog Design

Héctor Gómez

MSEE, Digital Design

Wilmer Ramírez

BSEE, Digital Verification

Andrés Amaya

MSEE, Mixed Signal Design

Rolando Torres

MSEE, Mixed Signal Design

Camilo Rojas

BSEE, Digital Design

Ckristian Durán

MSEE, Digital Design

Élkim Roa

PhD, Mixed Signal Design


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