ScopeFun is an affordable, open source, all-in-one instrumentation platform. It provides the following tools:
A Xilinx Artix-7 FPGA and a Cypress EZ-USB FX3 controller allow the board to interface with a PC while maintaining fast data rates. Samples are buffered using 512 Megabytes of DDR3 SDRAM. The main hardware specifications are:
The accompanying software runs on Windows, Linux, and Mac. It also provides a Server Mode that supports remote connections over an IP network. This allows the transfer of samples from nearly anywhere. It is also possible to interface with the hardware directly from Python scripts using the provided Python API.
The design is completely open source (software, firmware, and hardware) which facilitates the creation of highly customized test and measurement scenarios that are not possible with traditional equipment.
* The logic analyzer and digital pattern generator share the same 12 channels.
Two analog channels are available as oscilloscope inputs. Both analog inputs are protected against over-voltages up to +/- 50 V. Input coupling selection is available (DC, AC, GND) and is controlled through software. Input signals can be adjusted for gain and offset to allow measurements of voltages from 100 mV to 20 V (full scale) which gives a minimum input resolution of 0.098 mV. Each analog channel is sampled at 250 MSPS with 10-bit analog-to-digital converter (ADC). Two ADC’s can be configured for sampling in interleaved mode which provides a single channel sampling speed of 500 MSPS.
The ScopeFun also supports Equivalent Time Sampling (ETS) which provides a sampling speed of 2.0 GSPS for repetitive signals.
Two analog outputs are available as AWGs and can generate signals up to +/- 2 V. Both AWG outputs are protected against short circuit and over-voltages up to +/- 25 V. AWG outputs have 50 Ohm impedance which allows them to be used with a wide array of equipment. It is possible to select waveform shape, frequency, level and offset through the software. The chosen settings are immediately reflected in FPGA control registers. Digital samples are generated inside the FPGA and transferred to onboard dual digital-to-analog converters (DACs) at 200 MSPS per channel. Sine wave output is generated with the help of the CORDIC algorithm so that outputs of arbitrary frequency can be obtained. Other simple signals are derived from counters. Users can also provide custom waveform samples and upload them to the FPGA’s internal memory (BRAM). Scaling of the analog output (level and offset) is achieved with FPGA DSP blocks.
A 12-bit digital interface is sampled at 250 Mhz and logically divided into two 6-bit channel groups. Each channel group can be independently selected as input (to the logic analyzer) or as output (from the digital pattern generator). Digital interface voltage can be adjusted to as low as 1.25 V or as high as 3.3 V, though inputs are designed to accept up to 5 V. The selected interface voltage is also available on dedicated output pins and can be used as a low power voltage supply. Custom digital samples for the digital pattern generator can be uploaded to the FPGA, and an internal clock divider is available to control the output frequency. It is also possible to override individual outputs, at any time, with a logic ‘LOW’ or a logic ‘HIGH’.
The Python API gives direct access to ScopeFun functions directly from Python. This provides a simple way to create highly customized test scenarios without modifying the software source code. A Python script could be used to automate measurements, for example, or to post-process captured data. To demonstrate this feature, we have written a short Python script that captures samples from one of the analog inputs and plots a histogram of the captured signal.
|ScopeFun||PicoScope 3203D MSO||Red Pitaya||SmartScope||OpenScope|
|FPGA||Xilinx Artix-7 XC7A35T||-||Xilinx Zynq 7010||Spartan-6 XC6SLX4||-|
|USB||USB 3.0||USB 3.0||USB 2.0||USB 2.0||USB 2.0|
|RAM||512 MB DDR3||-||512 MB DDR3||8 MB SDR||-|
|Analog Bandwidth||100 MHz||50 Mhz||40 MHz||30 MHz||2 MHz|
|Max. Real-time Sampling Speed||500 MSPS||1 GSPS||125 MSPS||100 MSPS||6.25 MSPS|
|Equivalent Time Sampling||YES (2.0 GSPS)||YES (2.5 Gsps)||No||No||No|
|Memory Depth||128 MS||64MS||16 KS||4 MS||32 KS|
|Min. Voltage Sensitivity||0.098 mV||0.156 mV||0.122 mV||0.625 mV||-|
|Input coupling||AC, DC, GND||AC, DC||DC||AC, DC||DC|
|Arbitrary Waveform Generator|
|Update Rate||200 MSPS||20 MSPS||125 MSPS||50 MSPS||10 MSPS|
|Custom Signal Data Points||32 K||32 K||16 K||2 K||25 K|
|Output Range||±2 V||±2 V||±1 V||0 to +3.3 V||±1.5 V|
|Sampling Speed||250 MSPS||500 MSPS||12 MSPS||100 MSPS||10 MSPS|
|Memory Depth||128 MS||64 MS||1 MS||4 MS||32 KS|
|Digital Pattern Generator||YES||No||No||YES||No|
|Digital Pattern Generator Buffer Size||32 KS||-||-||2 KS||-|
|Update Rate||250 MSPS||-||-||100 MSPS||-|
* Digital channels share the same I/O pins.
Backers who support us at the Aluminum ScopeFun level will receive a fully assembled and ready-to-use ScopeFun with an aluminum enclosure. This enclosure protects the ScopeFun and provides shielding against EMI to help ensure low noise measurements.
We will be working with a local, European assembly house to manufacture the finished boards. This will allow us to keep an eye on the process and minimize delays caused by latency should adjustments need to be made during the manufacturing process.
All ScopeFun units will be delivered to Crowd Supply’s warehouse for final distribution to backers worldwide. For more information, please see this page about ordering, paying, and shipping.
We do not foresee any significant risks regarding ScopeFun production at this time.
We went through several PCB iterations and did extensive testing to ensure that the hardware is working as expected. On the software side, we will continue our work to resolve any bugs and make improvements.
When launching a new product, manufacturing delays are always a possibility, and component shortages or unforeseen issues during EMI/EMC tests could delay manufacturing. If we encounter any such challenges, however, we are confident in our ability to address them.
Funding ends on Jul 26, 2019 at 04:59 PM PDT (11:59 PM UTC)