Since the launch of the original HiFive1 and the FE310 in 2016, we have received lots of great community feedback. The FE310-G002 is an upgrade to the Freedom Everywhere SoC, that adds support for the latest RISC-V Debug Spec 0.13, hardware I²C, two UARTs, and power gating the core rail in low power sleep modes. Like the original FE310, the FE310-G002 features SiFive’s E31 CPU core complex, a high-performance, 32-bit RV32IMAC core with a 16 KB L1 instruction cache, a 16 KB data SRAM scratchpad, and hardware multiply/divide. Running at 320+ MHz, the FE310 is among the fastest microcontrollers on the market.
The HiFive1 dev board has also been upgraded. Powered by the FE310-G002, the new HiFive1 Rev B has wireless connectivity through an onboard Wi-Fi/Bluetooth module. The USB debugger has been upgraded to Segger J-Link, with support for drag & drop code download. In favor of driving GPIO directly from the FE310, the HiFive1 Rev B supports 3.3 V I/O only.
The FE310 is the first open source, commercially available RISC-V SoC. SiFive has contributed the FE310 RTL code to the open source community. Now you can see what’s inside the chip and completely understand how the hardware works. Take a look.
By releasing the RTL code, SiFive wants to encourage open source development of both software that runs on RISC-V, as well as new RISC-V-based hardware.
The RTL code empowers chip designers with the ability to customize their own SoC on top of the base FE310. For system architects, developers, or companies without chip design capabilities, SiFive’s "chips-as-a-service" can customize the FE310 to meet their unique needs.
With this second-generation version, the FE310 chip now has a built-in hardware I²C peripheral and an extra UART (two total), which opens the door to connecting to all sorts of third-party sensors, actuators, and other devices. In addition, the USB debug interface has been upgraded to Segger J-Link.
The FE310-G002 has an Always-On (AON) power domain powered from 3.3 V. Controlled by AON, the CPU core power rail (1.8 V) can be turned off in sleep mode and will be turned on upon detecting a wake event.
The HiFive1 Rev B board has both Wi-Fi and Bluetooth capabilities, thanks to a single-core ESP32 co-processor that serves as a wireless modem for the FE310-G002 processor.
|CPU||SiFive E31||SiFive E31|
|RISC-V Debug Spec||version 0.11||version 0.13|
|Low-power Sleep Mode||No||Yes|
|Always-on Domain||1.8 V||3.3 V|
|QSPI/SPI||1/1 with 3 chip selects||1/1 with 3 chip selects|
|Original HiFive1||HiFive1 Rev B|
|Processor||SiFive FE310-G000||SiFive FE310-G002|
|USB Debug||FTDI FT2232||Segger J-Link|
|Wireless Network||None||Wi-Fi & Bluetooth|
|I/O Voltage||3.3 V, level-shifted 5.0 V||3.3 V|
|Code Storage*||16 MB QSPI NOR Flash||4 MB QSPI NOR Flash|
|Form Factor||68 x 51 mm||68 x 51 mm|
* The original HiFive1’s 16 MB of code storage was overkill — there’s still plenty of room in 4 MB.
"HiFive1 Rev B by SiFive is now powered by the FE310-G002 and offers wireless connectivity via the on-board Wi-Fi/Bluetooth module."
"Since the Bay Area startup SiFive announced the release of their Freedom Everywhere 310 (FE310) system-on-chip (SoC) ... back in 2016, the RISC-V architecture has undergone what can only be called a renaissance."
"The revised version of the HiFive1 embedded development board from SiFive adds Wi-Fi and Bluetooth support on the Arduino-compatible board."
"Optimisation and power savings at the edge for IoT devices also necessitate that developers not be unnecessarily frustrated by walled-off gardens. Critically, The FE310 is the first open source, commercially available RISC-V SoC."
Produced by SiFive in San Mateo, CA.
Sold and shipped by Crowd Supply.
Get a single HiFive1 Rev B dev kit, featuring the FE310-G002, SiFive's second generation open source RISC-V 32-bit SoC.
San Mateo, CA · sifive.com
SiFive is the leading provider of processor cores, accelerators, and SoC IP to create domain-specific architecture based on the free and open RISC-V instruction set architecture. SiFive offers scalable, configurable processor cores pre-integrated with security, trace, and debug features for workload-specific accelerator designs. Founded by the inventors of RISC-V, SiFive has 15 design centers worldwide and backing from Sutter Hill Ventures, SK Hynix, Qualcomm Ventures, Western Digital, Intel Capital, Spark Capital, Osage University Partners, and Prosperity7 Ventures.