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Glasgow is a tool for exploring digital interfaces. It is designed for embedded developers, reverse engineers, digital archivists, electronics hobbyists, and anyone else who wants to communicate with a wide selection of digital devices while enjoying maximum reliability and minimum hassle. It can be attached to most devices without additional active or passive components, and it provides extensive protection from unexpected conditions and operator error.
The Glasgow hardware can support many digital interfaces because it uses reconfigurable logic. Instead of offering just a small selection of standard hardware supported interfaces, it uses an FPGA to adapt on the fly to the task at hand without compromising performance or reliability, even for unusual, custom or obsolete interfaces.
The Glasgow software is a set of building blocks designed to eliminate incidental complexity. Each interface is packaged into a self-contained applet that can be used directly from the command line or integrated into a more complex system. Using Glasgow does not require any programming knowledge, though it is much more powerful if you know a bit of Python.
Below are a few of the tasks that Glasgow already performs quite well:
Everything above can be done with only a Glasgow revC board, some wires, and – depending on the device under test – external power. No additional frontend circuitry is needed.
Glasgow Interface Explorer is written entirely in Python 3. The interface logic that runs on the FPGA is described using Migen (and is currently being ported to nMigen), which is a Python-based domain specific language. The supporting code that runs on the host PC is written in Python with asyncio. This way, the logic on the FPGA can be assembled on demand for any requested configuration, keeping it as fast and compact as possible, and code can be shared between gateware and software, removing the need to add error-prone “glue” boilerplate.
Glasgow would not be possible without the open source iCE40 FPGA toolchain, which is not only very reliable but also extremely fast. It is so fast that FPGA bitstreams are not cached (beyond what is necessary to avoid rebuilding the bitstream that is already on the device), as it only takes a few seconds to build one from scratch for something like an UART. When developing a new applet, it is rarely necessary to wait for the toolchain.
Implementing reliable, high-performance USB communication is not trivial – packetization, buffering, and USB quirks add up. Glasgow abstracts away USB. On the FPGA, applet gateware writes to or reads from a FIFO; on the host, applet software writes to or reads from a socket-like interface. On a modern PC, Idiomatic Python code can communicate at speeds up to USB 2 bulk bandwidth without additional effort. Moreover, this design is relatively future proof, as it can support different transports, such as Ethernet, without requiring changes to applet code.
Debugging new applets can be hard, especially where bidirectional buses are involved. Glasgow provides a built-in, cycle-accurate logic analyzer that can relate the I/O pin level and direction changes to commands and responses received and sent by the applet. The logic analyzer compresses waveforms and can pause the applet if its buffer is about to overflow.