We are thrilled to announce the launch of our crowdfunding campaign for simpleFE, which is a high-speed, low-cost, mixed-signal frontend. simpleFE is open hardware that leverages open source software to help your digital signal processing (DSP) and software-defined radio (SDR) projects succeed.
The main reason why we haven’t posted an update recently is
because we’ve been trying to get as much done as possible
before the beginning of the Chinese New Year celebrations.
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New: HealthyPi 6, Edgi-Talk, ManT1S, USB VSense; Coming Soon: SI-GRID, Pixel Pump 2, Sentinel Core; In Stock: Signaloid C0-microSD, SPIDriver, The New Essential Guide to Electronics in Shenzhen, uSDR
We now have most of the components with our assembly house in Taiwan. We are waiting for the long lead items and working closely with our suppliers to expedite the delivery. The key components are the Altera Cyclone IV FPGA and Rakon TCXO.
We have been busy building the inventory of components and parts for assembly of the LimeSDR boards. As mentioned in our previous manufacturing update, we have been working with our suppliers to expedite the delivery of the long-lead-time components: the FPGA and crucially, the TCXO.
Welcome to our fourth post-campaign update! In this update, we'll talk about: Shipping & production updates, downloading the User Manual, Artix A35 Production & Updates, and seeing us at COSADE, Black Hat USA, and more!
We're excited to announce the launch of the Icicle Kit: the first development board for Microchip's groundbreaking PolarFire SoC, the world's first FPGA and Linux-capable RISC-V system in a single chip. Together at last!
Wow! What a crazy month - from launching at the Teardown event in
Portland to wrapping up at Toorcamp in Seattle, it's been a thrill
running the NeTV2 crowdfunding campaign and getting in touch with
developers everywhere.
In a new post up on the Myriad-RF blog, Andrew announces the availability of the design and manufacturing files, plus FPGA project files, for the PCIe variant of LimeSDR.
Our team is hard at work adding features to the UltraMiner FPGA Developer Edition. We have routed TX and RX lanes for PCIe and improved GPIO performance by switching to a tighter pitch connector.
Welcome to our big post-campaign update! We've been delayed on getting this out to you, but not delayed on the important work of getting ChipWhisperer-Husky into your hands.
Lots of good updates & so far none of those dreaded supply chain delays. First, some quick highlights: